
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Power-Up Specifications
All functionalities and DC specifications are specified for a V DD ramp rate of greater than 1V per 100
ms (0V to 1.8V in less than 180 ms). If the VDD ramp rate is slower than 1V/100 μs, a hardware reset
is required. The recommended V DD power-up to RESET# high time should be greater than 100 μs to
ensure a proper reset. See Table 15 and Figures 24 and 25 for more information.
Table 15: Recommended System Power-up Timings
Symbol
T PU-READ1
Parameter
V DD Min to Read Operation
Minimum
100
Units
μs
T PU-WRITE
1
V DD Min to Write Operation
100
μs
T15.0 25016
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
T PU-READ
V DD
RESET#
0V
V DD min
V IH
T RECR
CE#
1328 F37.1
Note: See Table 2 on page 6 for T RECR parameter.
Figure 24: Power-Up Reset Diagram
?2011 Silicon Storage Technology, Inc.
26
DS25016A
06/11